Midterm Prep

37 exam questions mapped to course topics

Every question below is based on actual BME Computer Architectures midterm patterns. They are organized by topic so you can practice exactly what will be tested.

Total Questions

Midterm 1 Topics

Midterm 2 Topics

Weeks Covered

Exam Simulation

Practice exams with 7 questions each — timed, scored, and reviewed. Test yourself under real exam conditions.

Start

Midterm 1 Coverage

MT1

You are responsible for Weeks 1-6, 8

Week 1 Week 2 Week 3 Week 4 Week 5 Week 6 Week 8

ISA, Pipeline, Branch Prediction, OoO Execution, Cache

Midterm 2 Coverage

MT2

You are responsible for Weeks 7, 9, 10, 11, 12

Week 7 Week 9 Week 10 Week 11 Week 12

Memory Tech, Virtual Memory, I/O, Storage, Multiprocessor, SIMD

Expected Question Distribution

Estimated from patterns across past midterms — 7 questions, 10 points each, 70 total

Midterm 1

ISA & Instruction Encoding

W210 pts

Pipeline Scheduling & Hazards

W310 pts

Pipeline Stalls & Forwarding

W410 pts

Branch Prediction Analysis

W510 pts

Out-of-Order / Tomasulo

W610 pts

Cache Hit/Miss Calculation

W810 pts

Cache Design & Associativity

W810 pts

Total70 pts

Midterm 2

Memory Technology Calculations

W710 pts

Virtual Memory / Page Table

W910 pts

TLB & Address Translation

W910 pts

I/O Communication & DMA

W1010 pts

Storage Systems

W1110 pts

Bus Protocols (PCI/USB)

W1010 pts

Multiprocessor / SIMD

W1210 pts

Total70 pts

Most Tested Topics

How many times each topic appeared across past midterms

Cache Design & PerformanceMT1

Week 8

Sample MT1 (x2)MT1 (x2)MT1 Repeat (x2)

Pipeline Hazards & SchedulingMT1

Week 3 Week 4

Sample MT1 (x2)MT1MT1 Repeat (x2)

Virtual Memory & TLBMT2

Week 9

Sample MT2 (x2)MT2 (x2)MT2 Repeat

Branch PredictionMT1

Week 5

Sample MT1MT1MT1 RepeatMT1 Repeat

I/O Systems & BusesMT2

Week 10

Sample MT2MT2 (x2)MT2 Repeat

ISA & Addressing ModesMT1

Week 2

Sample MT1MT1MT1 Repeat

Out-of-Order ExecutionMT1

Week 6

Sample MT1MT1MT1 Repeat

Memory Technology (SRAM/DRAM)MT2

Week 7

Sample MT2MT2MT2 Repeat

Multiprocessor & SIMDMT2

Week 12

Sample MT2MT2MT2 Repeat

Storage (HDD/SSD)MT2

Week 11

MT2MT2 Repeat

Memory ProtectionMT2

Week 9

Sample MT2MT2 Repeat

Performance MetricsMT1

Week 1 Week 3

Sample MT1MT1

Midterm 1 Questions

Covers: ISA, Pipeline, Branch Prediction, OoO Execution, Cache

Sample Midterm 1Q1mediumWeek 1: Introduction & Performance

Performance Calculation

Calculate CPU execution times for two processors with different clock rates and CPI values. Determine which is faster and by how much.

Sample Midterm 1Q1mediumWeek 2: Instruction Set Architecture

ISA & Instruction Encoding

Encode a given MIPS assembly instruction sequence into binary/hexadecimal machine code. Identify instruction formats and field values.

Midterm 1Q1hardWeek 2: Instruction Set Architecture

ISA & Instruction Encoding

Decode hexadecimal machine code back to MIPS assembly. Determine addressing mode used by each instruction.

Midterm 1 RepeatQ1mediumWeek 2: Instruction Set Architecture

ISA & Addressing Modes

Analyze MIPS instructions, identify addressing modes, and calculate effective addresses for given register contents and memory values.

Midterm 1Q2hardWeek 3: Pipeline Basics

Pipeline Scheduling

Given an instruction sequence, draw the pipeline timing diagram and identify all hazards. Determine total execution time with and without stalls.

Sample Midterm 1Q7mediumWeek 3: Pipeline Basics

Pipeline Performance Calculation

Calculate effective CPI given instruction mix and stall frequencies. Determine pipeline speedup over non-pipelined execution.

Sample Midterm 1Q2hardWeek 4: Advanced Pipeline & Hazard Resolution

Pipeline Stalls & Forwarding

Given an instruction sequence, identify all data hazards, determine which forwarding paths resolve them, and count remaining stall cycles. Draw the pipeline timing diagram.

Midterm 1 RepeatQ2hardWeek 4: Advanced Pipeline & Hazard Resolution

Pipeline Scheduling & Forwarding

Reorder a given instruction sequence to minimize stalls. Draw pipeline timing for both original and scheduled versions.

Sample Midterm 1Q4hardWeek 5: Branch Prediction

Branch Prediction Analysis

Trace a 2-bit branch predictor through a given sequence of branch outcomes. Calculate misprediction rate and effective CPI impact.

Midterm 1Q4hardWeek 5: Branch Prediction

Branch Prediction with BTB

Analyze a program with a loop and conditional branches. Determine BTB hits/misses and prediction accuracy using a 2-bit counter.

Midterm 1 RepeatQ4mediumWeek 5: Branch Prediction

Branch Prediction Comparison

Compare 1-bit and 2-bit predictors on the same branch trace. Calculate misprediction rates for both and determine which is better.

Sample Midterm 1Q5hardWeek 6: Out-of-Order Execution

Out-of-Order / Tomasulo

Given a sequence of floating-point instructions and execution latencies, fill in the Tomasulo table showing issue, execute start, execute complete, and write result cycles for each instruction.

Midterm 1Q5hardWeek 6: Out-of-Order Execution

Tomasulo with ROB

Trace Tomasulo's algorithm with a Reorder Buffer. Show ROB entries, commit order, and register renaming. Handle a mispredicted branch.

Midterm 1 RepeatQ5hardWeek 6: Out-of-Order Execution

Register Renaming & CDB Conflicts

Trace Tomasulo's algorithm where two instructions want to write results in the same cycle. Determine CDB arbitration and final timing.

Sample Midterm 1Q6hardWeek 8: Cache Design

Cache Hit/Miss Calculation

Trace a sequence of memory accesses through a direct-mapped cache. For each access, determine hit or miss, and the final cache state.

Sample Midterm 1Q3mediumWeek 8: Cache Design

Cache Design & AMAT

Calculate tag, index, and offset bits for a given cache configuration. Then compute AMAT given hit time, miss rate, and miss penalty.

Midterm 1Q6hardWeek 8: Cache Design

Cache Hit/Miss with Set-Associative

Trace memory accesses through a 2-way set-associative cache with LRU replacement. Determine hits, misses, and calculate overall miss rate.

Midterm 1Q7hardWeek 8: Cache Design

Cache Total Storage & Multi-level

Calculate total storage (data + tag + valid + dirty bits) for a cache. Analyze a 2-level cache hierarchy and compute overall AMAT.

Midterm 1 RepeatQ6hardWeek 8: Cache Design

Cache Access Pattern Analysis

Analyze a loop that accesses an array. Determine the cache hit/miss pattern for the first and subsequent iterations.

Midterm 1 RepeatQ7mediumWeek 8: Cache Design

Cache Optimization

Given a cache with poor performance, analyze which configuration changes (block size, associativity, capacity) would most improve hit rate.

Midterm 2 Questions

Covers: Memory Technology, Virtual Memory, I/O, Storage, Multiprocessor

Sample Midterm 2Q1mediumWeek 7: Memory Technology

Memory Technology Calculations

Calculate DRAM access time, bandwidth, and refresh overhead for a given DRAM configuration. Compare SRAM and DRAM for a specific application.

Midterm 2Q1mediumWeek 7: Memory Technology

DRAM Timing & Bandwidth

Given a DDR4 module specification, calculate peak bandwidth, effective bandwidth considering refresh overhead, and compare with CPU memory demand.

Midterm 2 RepeatQ1mediumWeek 7: Memory Technology

SRAM vs DRAM Analysis

Compare the total area and access time of SRAM vs DRAM for a given capacity. Calculate the cost/bit ratio and determine which is more appropriate.

Sample Midterm 2Q2mediumWeek 9: Virtual Memory

Virtual Memory / Page Table

Given virtual/physical address widths and page size, calculate page table entries, PTE size, and total page table size. Handle a 2-level page table design.

Sample Midterm 2Q3hardWeek 9: Virtual Memory

TLB & Address Translation

Trace a sequence of virtual addresses through a TLB. Calculate TLB hit rate and effective memory access time (EMAT).

Midterm 2Q2hardWeek 9: Virtual Memory

Page Table Walk

Trace a 2-level page table walk for a given virtual address. Show how directory index and page table index are used to find the PFN.

Midterm 2Q3hardWeek 9: Virtual Memory

TLB Performance Analysis

Given TLB size, associativity, and an access pattern, determine TLB hit/miss sequence and calculate average translation time.

Midterm 2 RepeatQ2mediumWeek 9: Virtual Memory

Virtual Memory & Protection

Design a page table for given specifications. Explain how protection bits prevent unauthorized access between processes.

Sample Midterm 2Q4mediumWeek 10: I/O Systems

I/O Communication & DMA

Calculate the CPU time wasted with polling vs interrupt vs DMA for a given I/O scenario. Determine which method is best.

Midterm 2Q4hardWeek 10: I/O Systems

DMA Transfer Calculation

Given DMA controller specs (bus width, frequency, burst size), calculate transfer time and effective bandwidth. Account for bus arbitration overhead.

Midterm 2Q5mediumWeek 10: I/O Systems

Bus Bandwidth & Protocols

Calculate peak and effective bandwidth for a PCIe Gen 3 x8 link. Compare with USB 3.0 for a given workload.

Midterm 2 RepeatQ4mediumWeek 10: I/O Systems

Interrupt Handling & I/O

Calculate interrupt frequency and CPU overhead for a device generating interrupts at a given rate. Determine if interrupt coalescing helps.

Midterm 2Q6mediumWeek 11: Storage Systems

Storage Systems

Calculate HDD access time components and compare with SSD for random and sequential workloads. Determine break-even point.

Midterm 2 RepeatQ5hardWeek 11: Storage Systems

RAID Performance & Reliability

Calculate RAID 5 effective capacity, write penalty (read-modify-write), and MTTF. Compare with RAID 10.

Sample Midterm 2Q7hardWeek 12: Multiprocessor & SIMD

Multiprocessor / SIMD

Trace MESI protocol state transitions for a sequence of read/write operations by multiple processors. Identify bus transactions generated.

Midterm 2Q7mediumWeek 12: Multiprocessor & SIMD

Parallel Speedup & SIMD

Apply Amdahl's Law to determine speedup with P processors. Analyze when SIMD vectorization of a loop gives better performance than scalar execution.

Midterm 2 RepeatQ7hardWeek 12: Multiprocessor & SIMD

Cache Coherence Analysis

Given a multi-processor access trace, determine MESI states and count bus transactions. Calculate coherence overhead as percentage of total accesses.

Midterm Study Strategy

- Midterm 1 focuses on: ISA encoding, pipeline scheduling & hazards, branch prediction FSMs, out-of-order execution (Tomasulo), and cache hit/miss analysis
- Midterm 2 focuses on: SRAM/DRAM technology, virtual memory & page tables, TLB calculations, I/O & DMA, storage systems, bus protocols, and multiprocessor architectures
- Every midterm has exactly 7 questions worth 10 points each
- Practice with pen and paper — draw pipeline diagrams, trace cache accesses, calculate address translations by hand
- For cache questions, always identify: cache size, block size, associativity, number of sets, tag/index/offset bits
- For pipeline questions, draw the timing diagram and mark data hazards, control hazards, and forwarding paths

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