Dashboard/Block 1: Foundations/Week 2
Week 2Foundations

Instruction Set Architecture

We study Instruction Set Architectures in depth — the contract between software and hardware. Focus is on MIPS as a clean RISC example: R-type, I-type, and J-type instruction formats, addressing modes, and the process of encoding and decoding binary instructions.

Learning Objectives

Classify instructions by format (R, I, J) in MIPS
Encode and decode MIPS instructions to/from binary
Understand addressing modes: register, immediate, base+offset, PC-relative
Compare register, stack, and accumulator architectures

Key Concepts

ISA Design Principles

An ISA defines the instruction formats, data types, registers, addressing modes, and memory model. Key design choices include fixed vs. variable length instructions, number of operands, and how memory is accessed.

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    Register architectures (MIPS, ARM) keep operands in registers — fast but limited count

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    Stack architectures (JVM) use an implicit operand stack — compact but many memory accesses

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    Accumulator architectures (6502) have one implicit operand register

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    Orthogonality: any operation should work with any addressing mode

MIPS Instruction Formats

MIPS uses three instruction formats, all 32 bits wide:

  • -R-type: opcode(6) | rs(5) | rt(5) | rd(5) | shamt(5) | funct(6) — for register-register ALU ops
  • -I-type: opcode(6) | rs(5) | rt(5) | imm(16) — for loads, stores, branches, immediates
  • -J-type: opcode(6) | address(26) — for jumps
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    R-type: opcode=0, function code in funct field (e.g., add=0x20, sub=0x22, and=0x24)

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    I-type: immediate is sign-extended to 32 bits for arithmetic, zero-extended for logical

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    J-type: target = PC[31:28] concatenated with address field shifted left by 2

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    Branch offset in I-type is relative to PC+4, measured in words (multiply by 4 for bytes)

Addressing Modes

MIPS supports several addressing modes that determine how the effective address of an operand is computed:

  • -Register: operand is in a register
  • -Immediate: operand is a constant in the instruction
  • -Base + Offset: effective address = register + sign-extended offset (used by lw/sw)
  • -PC-relative: effective address = PC + 4 + offset×4 (used by branches)
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    Load/store use base+offset: lw $t0, offset($base)

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    Branch uses PC-relative addressing for position-independent code

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    Jump uses pseudo-direct addressing: top 4 bits from PC, rest from instruction

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    lui + ori pattern used to load full 32-bit constants

W1: Introduction & PerformanceW3: Pipeline Basics