Dashboard/Block 2: Pipeline & Execution/Week 4
Week 4Pipeline & Execution

Advanced Pipeline & Hazard Resolution

This week we learn techniques to resolve pipeline hazards without stalling: data forwarding (bypassing) and instruction scheduling. We also study the unavoidable load-use hazard that still requires one stall cycle even with full forwarding.

Learning Objectives

Explain how data forwarding eliminates most data hazard stalls
Identify forwarding paths: EX/MEM→EX, MEM/WB→EX
Recognize load-use hazards that require a mandatory stall
Reorder instructions to avoid stalls (pipeline scheduling)

Key Concepts

Data Forwarding (Bypassing)

Forwarding passes a result directly from where it's produced to where it's needed, bypassing the register file. Two main forwarding paths:

  • -EX/MEM → EX: result from ALU output forwarded to ALU input of next instruction
  • -MEM/WB → EX: result from memory/ALU forwarded to ALU input two instructions later

Forwarding eliminates stalls for most ALU-to-ALU RAW hazards.

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    Forwarding from EX/MEM pipeline register: value is available at the end of the EX stage

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    Forwarding from MEM/WB pipeline register: value is available at the end of the MEM stage

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    Forwarding hardware adds multiplexers before ALU inputs

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    Without forwarding, every RAW hazard between adjacent instructions causes 2 stall cycles

Load-Use Hazard

A load-use hazard occurs when a lw instruction is immediately followed by an instruction that uses the loaded value. Even with full forwarding, the data is not available until the end of the MEM stage — but it's needed at the start of the EX stage of the next instruction. This requires exactly one stall cycle (bubble).

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    lw produces its result at the end of MEM, but the next instruction needs it at the start of EX

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    One mandatory stall cycle even with full forwarding

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    If the using instruction is 2 or more slots away, no stall is needed

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    Pipeline scheduling can insert independent instructions into the bubble slot

Pipeline Scheduling

Pipeline scheduling (or instruction scheduling) reorders independent instructions to fill stall slots. The compiler or hardware rearranges instructions without changing program semantics to avoid hazards.

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    Move independent instructions into load-use bubble slots

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    Must preserve data dependencies (only reorder independent instructions)

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    Compiler scheduling is done at compile time — simpler hardware

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    Hardware scheduling (dynamic) is more flexible but complex

W3: Pipeline BasicsW5: Branch Prediction