I/O Systems
This week covers how the CPU communicates with I/O devices: programmed I/O, interrupt-driven I/O, and DMA (Direct Memory Access). We also study bus architectures including synchronous/asynchronous buses, arbitration, and protocols like PCI and USB.
Learning Objectives
Key Concepts
I/O Communication Methods
Three main methods for CPU-I/O communication:
- -Programmed I/O (Polling): CPU repeatedly checks device status register. Simple but wastes CPU cycles.
- -Interrupt-driven I/O: Device signals CPU when ready. CPU handles interrupt, transfers data. Good for infrequent transfers.
- -DMA: A DMA controller transfers data blocks between device and memory without CPU involvement. Best for large transfers.
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Polling: CPU is busy-waiting — simple but CPU can't do other work
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Interrupts: CPU is free between transfers but interrupt overhead per transfer
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DMA: CPU sets up transfer, DMA controller handles the rest. CPU overhead only at start/end
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DMA modes: cycle stealing (one word at a time), burst mode (entire block), transparent (only when bus idle)
Bus Architecture & Protocols
A bus is a shared communication link between components. Buses can be synchronous (governed by a clock) or asynchronous (using handshake protocol). Arbitration decides which device gets the bus when multiple devices compete.
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Synchronous bus: operations tied to clock edges — simple but limited by clock skew over distance
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Asynchronous bus: uses request/acknowledge handshake — more robust for long buses
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Bus arbitration: centralized (single arbiter), distributed (daisy chain), or priority-based
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PCI Express: serial, point-to-point lanes (1/2/4/8/16x), each lane ~1 GB/s (Gen 3)
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USB: serial bus, tiered star topology, USB 3.0 = 5 Gbps (SuperSpeed)