Dashboard/Block 1: Foundations/Week 3
Week 3Foundations

Pipeline Basics

Pipelining is the key technique for improving instruction throughput. We study the classic 5-stage MIPS pipeline (IF, ID, EX, MEM, WB), the three types of pipeline hazards (structural, data, control), and how pipelining affects CPI and overall performance.

Learning Objectives

Describe the five stages of the classic MIPS pipeline
Identify structural, data (RAW, WAR, WAW), and control hazards
Calculate pipeline speedup and understand pipeline overhead
Draw pipeline timing diagrams for instruction sequences

Key Concepts

Five-Stage Pipeline

The classic MIPS pipeline has five stages:

  1. -IF (Instruction Fetch): read instruction from I-cache using PC
  2. -ID (Instruction Decode / Register Read): decode instruction, read registers
  3. -EX (Execute): ALU operation or address calculation
  4. -MEM (Memory Access): load from or store to D-cache
  5. -WB (Write Back): write result to register file

Each stage takes one clock cycle. With pipelining, up to 5 instructions overlap execution.

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    Ideal pipeline CPI = 1 (one instruction completes per cycle)

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    Pipeline registers (IF/ID, ID/EX, EX/MEM, MEM/WB) hold intermediate values between stages

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    Pipeline speedup approaches the number of stages for long instruction streams

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    Clock cycle time is determined by the slowest pipeline stage

Pipeline Hazards

Hazards are situations that prevent the next instruction from executing in the next cycle:

  • -Structural hazards: two instructions need the same hardware resource simultaneously
  • -Data hazards: an instruction depends on the result of a previous instruction still in the pipeline
  • -Control hazards: the pipeline doesn't know the next instruction address (branches/jumps)
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    RAW (Read After Write) is the most common data hazard — true dependency

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    WAR (Write After Read) and WAW (Write After Write) are name dependencies — not a problem in simple in-order pipelines

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    Structural hazards are avoided by design (e.g., separate I-cache and D-cache)

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    Control hazards cause a pipeline flush on mispredicted branches (typically 1-3 cycle penalty)

Pipeline Performance

Pipeline performance is measured by how close the actual CPI is to the ideal CPI of 1. Stalls from hazards increase the effective CPI:

CPIpipeline=1+stall cycles per instruction\text{CPI}_{pipeline} = 1 + \text{stall cycles per instruction}

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    Pipeline throughput = 1 instruction per cycle (ideal)

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    Latency of a single instruction increases with pipelining (k cycles vs 1 cycle)

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    Throughput is what matters for overall performance, not single-instruction latency

W2: Instruction Set ArchitectureW4: Advanced Pipeline & Hazard Resolution